Schematic Implementation Of High-Speedvlsi Authenticated Encryption For Gcm Architecture

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K. Raghu , Eswararao B , k vamsi Krishna , Paparao Nalajala , K saikumar

Abstract

High-speed VLSI authenticated encryption for GCM architecture is discussed in this article, which offers superior security and resource efficiency as compared to current standards. With an authenticated encryption system using a key scheduling method, you can ensure privacy and integrity on a regular basis. S-Box is used as a replacement for bits after the pre-processing step for preserving all bits in the register. Random number (the counter) is used in Counter mode, where each block of text encryption is altered. Counter mode uses random number. Finally, Encryption is used to encrypt the shifted bits. The ISE design tool from Xilinx 14.7 was used to execute this project, which produced outputs like the RTL schematic, the technology schematic, and the output waveforms in great detail.

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