Design and implementation of two-dimensional crossbar switch scheduler for SoC using quantum dot cellular automata and system Verilog

Abstract

Intelligent Arbiter circuit designed at quantum level is a solution for high-speed data switching circuits with non-blocking properties and miniaturization of the digital circuits at nano-level. In this paper a two-dimensional arbiter design has been proposed using quantum dot cellular automata. The circuit provides a congestion free network for data switching from any in-port to allocated out-port. In the paper a 3x3 arbiter circuit has been designed and analysed using QCA designer software. The paper also presents the design of same arbiter circuit using CMOS technology. To establish a logical discrimination highlighting the prominent features of low power requirements, very less area and high speed QCA circuits a comparison has been made between the two technologies. Also, the paper presents a more factual clock distribution to ease the practical realization (2-DW clocking) of QCA design of the presented grant allocate scheduler using QCA and results have been reported.