DESIGN OF THE 4 BIT RIPPLE CARRY ADDER USING DOMINO LOGIC AND CLOCK DELAYED DUAL KEEPER DOMINO CIRCUIT

Abstract

Today in the modern world, the technologies have been developing in designing the CMOS VLSI circuits by optimizing the leakage power, propagation delay in the deep sub-micron technologies. In few decades back power and delay consumption is more in the implementation of the transistor level design. The consumption of area increases similarly it increases its delay and energy efficiency. To overcome these major challenges, the DLC is proposed. The DLC consists of the precise keeper control which significantly increases the action of the operation. The positive feedback circuit is connected by a feedback to keeper circuit excessively to propagate the delay variance to the circuit. Over here standard high-speed clock delayed dual keeper is proposed with the keeper circuit that is made up of two keeper devices. This CDDK impressively bring down the power and thereby the rate of the circuit is elevated. By the CDDK the basic gates are implemented and analyzed the consumption of power and delay variability against the conventional domino logic by Monte-Carlo simulations. Additionally, the Monte-Carlo simulation is for the 4-bit ripple carry adder implementation and the reduction of energy efficiency and delay variability are demonstrated. The result comparison is done in case of the prosaic domino logic circuits. Analysis of the circuits is fulfilled by the cadence virtuoso tool by using 90nm technology.