A Review on RAM Cell Structures in QCA

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Amanpreet Sandhu, Parminder Singh, Archana Goel


CMOS circuit designs are scaling down from 6nm to 7nm in area but one cannot continue to follow Moore’s Law because the transistor size is now reaching to its physical limits. New techniques like Quantum-Dot-Cellular-Automata which uses the position of electrons confined with-in a QCA cell to represent the logic state of a memory cell is being utilized. The two types of Quantum based memories are Parallel memory and serial RAM memory. These QCA memories are based upon memory-in-motion paradigm that is memory logic should keep in motion by using QCA cells. Parallel memory architecture design in QCA offers low latency at the cost of reduced density. Parallel memory utilizes one-bit per memory cell like the traditional CMOS Random Access Memory (RAM) design, but in QCA such memory design offers repetition of the Write-Read circuitry for each RAM-cell or a memory bit. It increases the hardware in terms of number of QCA cells, clocking zones and control cells. This structure offers fast operations at the cost of reduced density.

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