Energy Efficient 1- Bit Comparator Design in Quantum Dot Cellular Automata

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Amanpreet Sandhu, Parminder Singh, Amanpreet Kaur, KR Ramkumar


Designing of digital circuits at nano level faces serious challenges like power dissipation, package density and physical barriers in CMOS. The researchers investigate other possible nanotechnologies having same capacities. Quantum Dot Cellular Automata (QCA) technology eliminates above said challenges. In this paper, QCA based single layer 1-bit comparator structure has been proposed. The proposed structure is efficient in occupational area, cell count, latency and Quantum Cost. The proposed comparator circuit has 0.24% improvement in cell count, 0.75% improvement in latency and 0.9% improvement in quantum cost. The energy dissipation analyses of proposed comparator have been calculated at tunneling energies of 0.5 Ek, 1.0Ek and 1.5Ek. The proposed comparator design dissipated4.98 % less energy at 0.5 Ek, 1.76 % less energy at 1.0Ek and 8.58 % less energy at 1.5Ek. as compared to the existing designs in literature. As a result, proposed designs are often found in various digital logics that require a small amount of space and low power consumption.

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